1. Field of Invention
The present invention relates to a driving circuit for a display device. More particularly, the present invention relates to a driving circuit for a display device without need for an output enable signal, thus saving energy consumption.
2. Description of Related Art
Conventional driving circuit for a display device comprises a gate driver and a source driver. Both the gate driver and the source driver comprise a trigger signal generating circuit. In the gate driver, the trigger signal generating circuit, such as, used as a scanning circuit, is used to generate a gate on/off signal for controlling the on/off of pixels. Whereas, in the source driver, the trigger signal generating circuit is used as a shift register for generating a plurality of trigger signals for triggering a data latch.
Conventional scanning circuits perform a logic (AND) operation on a signal generated by a shift register and an output enable signal OE to achieve the effect of separating scanning signals of two neighboring scanning stages of the scanning circuit, thus avoiding display errors caused by neighboring scanning signal lines being turned on simultaneously. The circuits of each scanning stage of a conventional scanning circuit are shown in FIG. 1.
FIG. 1 is a circuit diagram of each scanning stage of the conventional scanning circuit. Referring to FIG. 1, the circuit includes a first tri-state inverter 101, a first inverter 102, a second tri-state inverter 103, a third tri-state inverter 104, a second inverter 105, a fourth tri-state inverter 106, an NAND gate 107, and a third inverter 108. Each tri-state inverter has a clock input end and an inversion clock input end.
The first tri-state inverter 101 receives an input signal IN generated by the previous scanning stage (however, the input signal IN of the first scanning stage is an external input signal input from the outside of the scanning circuit) and performs a tri-state inversion on the input signal according to a clock signal CK and an inversion clock signal CKB and then outputs it. The inversion clock signal CKB is obtained by inverting the clock signal CK. The actions of the tri-state inversion are described as follows. If the input signal IN is logic 1 (i.e., high potential) and the clock signal CK is also logic 1 at this time, the first tri-state inverter 101 inverts the input signal IN to be logic 0 (i.e., low potential). However, if the clock signal CK is logic 0 at this time, the first tri-state inverter 101 keeps the input signal IN to be logic 1. If the input signal IN is logic 0 and the clock signal CK is also logic 0 at this time, the first tri-state inverter 101 inverts the input signal IN to be logic 1. However, if the clock signal CK is logic 1 at this time, the first tri-state inverter 101 keeps the input signal IN to be logic 0. The true value of the tri-state inversion is described as follows.
Input Signal INClock Signal CKOutput Signal of Tri-State Inverter001010101110The actions of the tri-state inversion in the following refer to the action of the first tri-state inverter 101 as shown in FIG. 1 and will not be described again.
The first inverter 102 receives an output of the first tri-state inverter 101, performs an inversion on the output of the first tri-state inverter 101, and then outputs it. The second tri-state inverter 103 performs the tri-state inversion on the output of the first inverter 102 according to the clock signal CK and the inversion clock signal CKB and then outputs it. An output of the second tri-state inverter 103 is also fed back to the input of the first inverter 102. The third tri-state inverter 104 performs the tri-state inversion on the output of the second tri-state inverter 103 according to the clock signal CK and the inversion clock signal CKB and then outputs it. The second inverter 105 receives the output of the third tri-state inverter 104, performs the inversion on the output of the third tri-state inverter 104, and then outputs it. The fourth tri-state inverter 106 also performs the tri-state inversion on the output of the second inverter 105 according to the clock signal CK and the inversion clock signal CKB. The output of the fourth tri-state inverter 106 is also fed back to the input of the second inverter 105. The output signal of the fourth tri-state inverter 106 is the input signal of next scanning stage.
Then, a logic operation is performed on the output of the second inverter 105 and the output enable signal OE by the NAND gate 107 and the third inverter 108, so as to generate a scanning signal OUTPUT1. The scanning signal OUTPUT1 is the signal generated by the first scanning stage and is used for the display unit (pixel) in the driving panel. Thus, scanning signals OUTPUT1-OUTPUTN not being overlapped one another can be obtained. The scanning signal OUTPUTN represents the scanning signal generated by the n-th scanning stage. The relation between the output enable signal OE and the scanning signal output by each scanning stage is illustrated by the use of the scanning signals output by five continuous scanning stages, as shown in FIG. 2.
FIG. 2 shows waveforms of the scanning signals output by five continuous scanning stages of the conventional scanning circuit. Referring to FIG. 2, IN as shown in FIG. 2, indicates an external input signal; CK indicates a clock signal; OE indicates an output enable signal; and OUTPUT1-OUTPUT5 indicates the scanning signals output by the first scanning stage, the second scanning stage, . . . , and the fifth scanning stage. It can be known from the FIG. 2 that after the pulse (201, as shown in FIG. 2) of the external input signal IN is input into the scanning circuit, the time difference between every two scanning signals (202 and 203, as shown in FIG. 2) in the scanning signals OUTPUT1-OUTPUT5 output by the first scanning stage, the second scanning stage, . . . , and the fifth scanning stage, is equal to the time difference between two pulses of the output enable signal OE (204 and 205, as shown in FIG. 2). The relationship among the pulses 202, 203, 204, and 205 is indicated by two dot lines (206 and 207, as shown in FIG. 2). Moreover, the pulse width of each scanning signal is also equal to the pulse width of the output enable signal OE. The pulse 208 and pulse 201 are the pulse of the external input signal IN.
However, it can be known from the FIG. 2 that the output enable signal OE are required to prevent the neighboring scanning signals from being overlapped according to the conventional technology, thus causing additional power consumption.